The present invention relates generally to memory devices and in particular the present invention relates to a non-volatile flash memory interface.
A typical Flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge in the floating gate.
A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory. SDRAM synchronizes itself with a CPU""s bus and is capable of running at 100 MHZ, about three times faster than conventional FPM (Fast Page Mode) RAM, and about twice as fast EDO (Extended Data Output) DRAM and BEDO (Burst Extended Data Output) DRAM. SDRAM""s can be accessed quickly, but are volatile. Many computer systems are designed to operate using SDRAM, but would benefit from non-volatile memory.
Advances in DRAM interfaces has resulted in double data rate (DDR) DRAMs. These memory devices provide data communication that is synchronized to both rising and falling edges of a clock signal. While DDR DRAMs provide for fast data communications, the data is stored in a volatile manner. Likewise, Rambus memory devices, such as RDRAM, provide a packet based alternative high-speed memory choice. The RDRAM provides similar operations as the DDR DRAM, and is volatile in nature.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a non-volatile memory that can communicate at fast DRAM speeds.
The above-mentioned problems with non-volatile memories and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a flash memory comprises an array of non-volatile memory cells, data connections, an interconnect configuration compatible with a rambus dynamic random access memory (RDRAM), and output circuitry to provide output data on the data connections on rising and falling edges of a clock signal.
In another embodiment, a flash memory comprises an array of non-volatile memory cells, data connections, a clock signal connection to receive a clock signal, and an interconnect configuration compatible with a rambus dynamic random access memory (RDRAM). Output circuitry provides output data on the data connections on rising and falling edges of the clock signal, and input circuitry receives input data on the data connections on rising and falling edges of the clock signal.
A method of reading a flash memory comprises providing a read command, providing memory cell addresses, reading first and second data words from non-volatile memory cells, outputting the first data word on a rising edge of a clock signal following a rambus dynamic random access memory (RDRAM) compatible format, and outputting the second data word on the falling edge of the clock signal following the rambus dynamic random access memory (RDRAM) compatible format.
In yet another embodiment, a flash memory comprises an array of nonvolatile memory cells having bit lines couplable to the non-volatile memory cells, sense amplifier circuitry coupled to the bit lines to detect a differential voltage between the bit lines, and pre-charge circuitry coupled to pre-charge the bit lines to first and second voltage levels to provide an initial differential voltage prior to sensing a memory cell. The memory includes data connections, a clock signal connection to receive a clock signal, and has an interconnect configuration compatible with a rambus dynamic random access memory (RDRAM). Output circuitry provides output data on the data connection on rising and falling edges of the clock signal.